Avery Design Debuts QEMU Virtual Host to SystemVerilog PCIe VIP HW-SW Co-simulation Solution for Pre-silicon System-level Simulation of NVMe SSD and PCIe Designs

TEWKSBURY, Mass.--(BUSINESS WIRE)--Avery Design Systems, leader in functional verification solutions today announced the pre-silicon system simulation solution of NVMeTM SSD and PCIe® designs using QEMU virtual host to SystemVerilog PCIe VIP co-simulation thus enabling the functional validation of complete NVMe and PCIe hardware-software SoC designs using industry standard conformance and performance benchmarking software applications running in Linux and Windows® environments.

“Early HW-SW integration and verification accelerates the development schedule and reduces bug fix times and iterations dramatically,” said Chris Browy, VP sales and marketing of Avery Design Systems. “We are pleased to expand the capability of our industry leading, SystemVerilog-based PCIe and NVMe VIP to support virtual host prototyping and address the needs of both hardware and software design teams.”

Co-simulating the actual SoC RTL with a QEMU open software virtual machine emulator environment running any number of Linux or Windows OS builds allows software engineers to natively develop and build any of their custom firmware, drivers, and applications and run them unaltered and debug software issues using standard debuggers (GDB and KGDB) as part of a comprehensive validation process of the SoC operation against the cycle accurate and detailed SystemVerilog RTL representation of the hardware. In a complementary manner, HW engineers can evaluate how their SoC performs through executing PCI BIOS and expansion ROM code, OS boot, and custom driver initialization sequences in addition to running real application workloads and utilizing the full PCIe and NVMe VIP protocol aware debugging features to investigate any hardware related issues.

Hardware or software design iterations can be turned around and evaluated rapidly and enable a much smoother transition from simulation to FPGA prototyping wherein the SoC design can go through comprehensive stress and interoperability testing.

System bring-up and validation using standards-based conformance and interoperability testing is now feasible across a wide range of designs - NVMe SSDs, smart NICs, PCIe switches and retimers, and a myriad of other PCIe endpoint-based peripherals. Examples include:

  • NVMe SSD validation requires executing the UNH-IOL INTERACTTM test software in addition to other performance benchmarking applications such as FIO, PMark8, and CrystalDiskMark.
  • PCIe compliance requires passing the PCI-SIG® PCIeCV and interoperability tests at a PCI-SIG Compliance Workshop.

“Supporting IOL INTERACTTM in a QEMU/PCIE VIP system-level co-simulation platform for in-house testing at the pre-silicon level gives IOL INTERACT users great confidence that their products will meet the NVMe Integrator's list requirements when submitted for testing,” said David Woolf, Senior Engineer, Datacenter Technologies, UNH-IOL. “We are pleased to collaborate with Avery to have this solution supported for our latest IOL INTERACT release deploying the UNH-IOL NVMe Conformance and UNH-IOL NVMe Interoperability test plans.”