Comparing Measurements of High Speed Serial Interfaces

The priorities and specifics of physical limitations differ between standards. For instance Mobile Industry Processor Interface (MIPI) physical layer (PHY) specifications prioritize low power consumption and low electromagnetic interference (EMI) whereas an enterprise storage specification such as Serial Attached SCSI (SAS) focuses on high bandwidth and reliability. The MIPI protocols that are tested at the UNH-IOL are designed for video streaming while SATA is for transmission of Block Storage data. Both send bursts of data with headers and footers to manage erroneous bits. In MIPI the breaks between bursts are relatively short because one line of pixels is usually contained in one burst. After each MIPI burst there is also a break where the transmitter stops sending data, and the receiver stops terminating the signal line, to save on power. The MIPI PHY Specification specifies the timings and voltage levels necessary for entering and exiting this low power mode. SATA on the other hand, does not take breaks between bursts. Once one frame is finished, another is sent. If no data needs to be sent, idle data is shared to maintain the connection.

One thing that Ethernet, SATA, MIPI, telephones, HDMI, DisplayPort, USB, PCIe, and even most audio transmission over copper have in common is that they use balanced differential signaling. Differential signaling sends one signal down two wires with opposite voltages. This is referred to as balanced because at any given point the sum of the voltages on both wires should be constant. Since all wires act as antennas, the two signals’ fields cancel each other out and avoid interfering with other nearby pairs as long as the pair of wires are kept close together. The proximity of the wires also results in outside interference affecting both lines the same way. This means that when the receiver rebuilds the signal by subtracting both lines, the interference is subtracted out as well.

Single-ended coaxial cables are used in testing because of their superior shielding against outside noise, but are larger and more expensive. The size and cost of these cables is not ideal for small consumer devices or PCBs. Any imbalance in a differential pair results in EMI. MIPI pays close attention to different types of imbalances to make sure that the interference coming from the traces on the phone’s PCB does not affect the radios. A wire sending a 1Gbps signal can be modeled as a 500MHz square wave. The spectrum of this looks like a sinc function with nulls at multiples of 500MHz. Most of the energy is between 0Hz and 1.5GHz. This is right where cellular radio and GPS spectrums are located. This is particularly problematic for GPS as the signal strength received is typically below -120dBm. MIPI PHY testing checks that a differential 0 and 1 both have the same voltage level because if one bit is smaller than the other the line becomes imbalanced. The common mode signal is also heavily scrutinized in MIPI. The common mode signal is the average of the two. If the signals were perfect inversions of each other the common mode would be a constant signal. Analyzing the frequency components of the common mode signal is a good indicator of what frequencies will come out of the differential pair to the rest of the system. If one line has a rising or falling edge that is slower than the other, there will be a high frequency spike. If one signal path is longer or has more impedance than the other then the edges will also be out of alignment causing an artificially higher common mode power spectrum. Care must be taken during test setup so the lines are matched in length and impedance from the DUT to the probe. Making sure the common mode signal does not have significant frequency components between 50MHz and 450MHz (low frequency) or above 450MHz (high frequency) helps assure that the traces carrying these signals won’t interfere with nearby radios.

SATA does not heavily emphasize balanced transmission line tests but does scrutinize the reliability of the signal comprehensively. The cable that SATA signals are sent over is higher loss than the short traces typically used in mobile devices. SATA signals run at higher bitrates so the error rate and jitter, jitter is the variation in timing of a bit edge, are tested to make sure performance is not affected by the PHY implementation. Error detection in a testing environment is tricky because an error may never be observed over a reasonable amount of time but something still needs to be said about the likelihood of an error. The details of the statistics are out of the scope of this blog but it is generally accepted that if we want an error rate of at most 106 with a confidence of least 95%, then we need to observe 3*106 bits without an error. Jitter is often confused with a changing bitrate but the jitter will average out when the bitrate consistency is examined. The details of jitter are also out of the scope of this blog but it is tested because of the nature of high bandwidth data transmission. The cable has an inherent amount of capacitance that won’t be easily changed but as data is sent at higher bitrates the time a bit sits at the “high” or “low” voltage decreases while the time it takes to charge the cable up stays the same. This cable charging causes a signal to look more like a sine wave than a square wave, and the exact time an edge is clocked by the receiver can be the difference between a valid and an erroneous bit.

Paul Willis, SATA & MIPI Technician