10 Gigabit Ethernet Test Vectors

Test Vectors are data to be applied at one standard-defined interface with expected results at another standard-defined interface. For example, a test vector could be provided for the XSBI receive path below the WIS, and expected result vectors could be provided for the XGMII receive layer or XAUI layer.

Through vendor feedback, these test scenarios are expected to evolve and improve, providing the 10 Gigabit Ethernet community with a shared resource of expected behavior.

Public Test Vectors

Private Test Vectors (Members Only)

Test scenarios that do not solely verify the bit-ordering of a vendors interface are under development, and will only be made available to 10 Gigabit Ethernet Consortium members. Provided sufficient interest, and a reasonable set of test scenarios, these scenarios may be developed into Verilog's test bench to reduce the burden on the members.

Please contact us directly to find more information about the private test vectors.